The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to metal cap integration on interconnect structures.
With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
Silicon-based devices typically include multiple interconnect metallization layers above a device (front-end-of-line/FEOL) layer that contains field-effect transistors (FETs), memory devices, or other structures. Middle-of-line (MOL) processing includes steps typically used for fabricating metal contacts for logic circuitry components such as field-effect transistors (FETs), resistors, diodes, and capacitors. Interlayer dielectric (ILD) is used to electrically separate closely spaced interconnect lines. Lower-k interlayer dielectrics are associated with lower power consumption and reduced cross-talk. Back-end-of-line (BEOL) processing involves the creation of metal interconnecting wires that connect the devices formed in FEOL processing to form electrical circuits. The wires are electrically isolated by dielectric layers.
A thin barrier layer (not shown), which is typically about 25-75 nm thick and which comprises, for example, silicon nitride, is deposited over the FEOL layer (not shown). This is followed by deposition of one or more dielectric layers and one or more cap layers, forming a MOL dielectric layer 22 as shown in FIG. 8. The MOL dielectric layer 22, including the cap layer(s), may contain any suitable dielectric material(s) including but not limited to: silicon dioxide, silicon nitride, silicon oxynitride, boron doped phosphorus silicate glass (BPSG), and phosphosilicate glass (PSG). In some embodiments, the MOL dielectric layer(s) and the cap layer(s) contain BPSG or undoped low temperature oxide that is formed by any suitable dielectric deposition processes, including, but not limited to: high density plasma deposition (HDP) or plasma-enhanced chemical vapor deposition (PECVD). The MOL dielectric/cap layer(s) typically function to act as barriers between the transistors in the FEOL layer and metal layers to be deposited subsequently, so as to prevent migration of the metal species into active regions of the transistors and to protect the transistors against potential metal contamination. The layer may also function as a mask for forming deep trenches in the semiconductor substrate of the FEOL layer for subsequent fabrication of the trench capacitors. The MOL dielectric layer 22 may have a thickness ranging from about 5000 Å to about 7000 Å or greater, depending on the specific application requirements to provide a dielectric cover for the transistors or other logic circuitry components comprising the FEOL layer during and metal contact fabrication process.
Trench openings are conventionally formed in the MOL dielectric layer 22 by using photolithography and etching steps. Specifically, a photoresist (not shown) is applied over the MOL dielectric layer 22. The photoresist can be applied by any suitable technique, including, but not limited to coating or spin-on techniques. A mask (not shown), which is patterned with shapes defining trench openings (and possibly contact holes) to be formed, is provided over the photoresist, and the mask pattern is transferred to the photoresist using a photolithographic process, which creates recesses in the uncovered regions of the photoresist. The patterned photoresist is subsequently used to create the same pattern of recesses in the MOL dielectric layer through conventional etching typically used for forming trenches and contact holes. The etching selectively removes a portion of the MOL dielectric layer and stops above the FEOL layer. The depth of the trench openings can be controlled by using a timed etching process. Alternatively, the dielectric layer may include multiple layers that may be selectively etched. In such a case, the etch process selectively removes the upper layer(s) of the MOL dielectric layer 22, stopping at a lower layer thereof that adjoins the FEOL layer and forms an etch stop. After formation of the trench openings, the photoresist may be stripped by ashing or other suitable process from the MOL dielectric layer 22.
A barrier layer 26 is conformally deposited on the structure, thereby lining the trenches formed within the dielectric layer 22. The barrier layer is formed from a work function setting material such as titanium nitride, TaN or WN. A metal interconnect layer 28 is deposited on the barrier layer 26 using, for example, chemical vapor deposition. The structure is planarized using a process such as chemical mechanical planarization (CMP). Referring again to FIG. 8, a metal cap layer 30 is selectively deposited on the metal interconnect layer 28 within the trenches. For example, metals such as cobalt, ruthenium or manganese may be deposited using chemical vapor deposition or atomic layer deposition to form the cap layers. The selectivity of metal cap deposition can be problematic and result in metal residue 30A. Post-deposition cleaning is accordingly required to ensure there is no leakage or degradation resulting from the possible metal residues on a structure 20 as shown in FIG. 8.
In an alternative prior art approach, a structure 40 as shown in FIG. 9A is obtained using some of the techniques described above. The structure 40 includes a trench 44 within a MOL dielectric layer 42. The trench 44 contains a copper interconnect 46 formed on a barrier layer. A low-k, silicon carbide-based film 47, such as a barrier low-k (BLOk) film, is compatible with the copper damascene process and can function as a barrier/etch stop layer. The copper interconnect 46 is then recessed as shown in FIG. 9B so that the exposed top surface thereof is beneath the plane of the silicon carbide film 48 and underlying MOL dielectric layer 42. As shown in FIG. 9C, a self-aligned deposition of a metal cap layer 49 of, for example, ruthenium (Ru) seals the top surface of the structure, including the copper interconnect 46. The structure is subjected to further chemical mechanical planarization down to the top surface of the silicon carbide film 47, as shown in FIG. 9D. The metal cap layer 49 thereby protects the interconnect structure from, for example, downstream etch processes and provides electrically conductive surfaces on the MOL dielectric layer.